Computer Science Colloquium
Formal Verification of Verilog HDL with Yosys-SMTBMC and SymbiYosysMon 06.03.2017, 13:00, 120 minutes
Science Park 2, S2 Z74
AbstractYosys is a free and open source Verilog synthesis tool and more. In this presentation we discuss Yosys-SMTBMC, a Yosys-based formal verification flow that can use any SMT-LIB2 solver as back-end engine, and SymbiYosys, a uniform front-end for various Yosys-based formal flows, including Yosys-SMTBMC and flows utilising AIGER-based engines.
BioClifford Wolf develops open source software, has been teaching at Metalab and collaborates and publishes with the Institute of Computer Technology, of the Vienna University of Technology. He is particularly interested in developing high quality open source solutions for Electronic Design Automation (EDA), which are software tools for industrial hardware design.
Invited by Prof. Dr. Armin Biere, Institute of Formal Models and Verification
The Computer Science Colloquium is organized by the Department of Coputer Science at JKU, the Österreichische Gesellschaft für Informatik (ÖGI) and the Österreichische Computergesellschaft (OCG).